Products in Bangalore (142481 results)

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UVM

This UVM hands-on course begins with a good overview of UVM methodology, explaining the concepts like agents and UVCs with various examples like AHB UVCs and SOC UVM testbenches. With this overview it walks you through all the concepts like UVM TB framework, base class library, factory, sequences, phases, reporting mechanism, TLM ports, virtual sequences, events, call backs, UVCs, Scoreboard, UVM environment, etc and guide you to do the lab exercises to understand all the concepts very well.

SystemVerilog For Verification

This Systemverilog language course explains all the language data types and concepts, especially how we can use all the language features to create a class-based verification environment. It explains all the data types, language features like interfaces, OOP, randomisation, functional coverage, etc. in detail and trains you extensively on creating the class-based verification environment.

VLSI Verification

VLSI Verification Course starts with a good overview of functional verification methodologies and SystemVerilog language and then it explains the nuts and bolts of building class-based verification environment using SystemVerilog HDVL in detail. Then it gives a good overview of Universal Verification Methodology. This verification course is completely based on a standard testbench architecture which can be used for creating SystemVerilog testbenches and at the same they can be easily migrated to

VLSI Design Methodologies

VLSI Design Methodologies course is a front end VLSI course which imparts the VLSI Design Flow, Digital Design and RTL programming using Verilog HDL This course starts with an overview of VLSI and explains the VLSI technology, SoC design, Moore’s law and the difference between ASIC and FPGA. With this overview, it walks you through all the steps of complete VLSI Design flow and explains every step in detail. Then it covers the complete digital design, combinational, sequential and FSM desig

Verilog HDL

This Verilog course covers the coding for synthesis and simulation. It explains the concepts of hardware description language and basic concepts like data types and operators. Then it explains the advanced concepts like assignments, procedural blocks, synthesis coding style and testbench coding, in detail with various examples. Doing the labs and projects will make you a hands-on RTL programmer

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